Integrated circuit wafer fabrication facilities adhere to strict standards in each stage of producing integrated circuits as wafer technologies become more advanced. Even with the strict standards, slight variations occur between wafer lots, wafers within a lot, dies within a wafer, and even transistors within a die. These on-chip variations (OCV) may be caused by variations in impurity concentration densities, oxide thicknesses, diffusion depths, voltage, temperature, etc.
When an integrated circuit designer does not budget enough timing margin for these “on chip” variations, production yield is reduced due to functional failures and/or timing failures. Static timing analysis is typically performed during an integrated circuit's “design synthesis” phase that checks whether all “paths” within the design meet stated timing criteria. In many cases, static timing analysis is conservative in the sense that it over-estimates the delay of long paths in the circuit and under-estimates the delay of short paths in the circuit. However, in many cases due to performance requirements, the integrated circuit designer is not able to allow an increased amount of timing margin in an integrated circuit.